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參數(shù)資料
| 型號(hào)： | XC9536XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | FastFLASH High-Performance CPLD(FastFLASH 高性能復(fù)雜可編程邏輯器件) |
| 中文描述： | FastFLASH高性能的CPLD（FastFLASH高性能復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 143K |
| 代理商： | XC9536XL |
R
June 7, 1999 (Version 1.5)
5-15
FastFLASH XC9500XL High-Performance CPLD Family
5
CMOS levels by connecting the device output voltage sup-
ply (V
CCIO
) to a 3.3V or 2.5V voltage supply.
Figure 11
shows how the XC9500XL device can be used in 3.3V only
systems and mixed voltage systems with any combination
of 5V, 3.3V and 2.5V power supplies.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of
t
SLEW
) under user control. See
Figure 12
.
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of
the global output enable signals (GTS), always “1,” or
always “0.” There are two global output enables for devices
with 72 or fewer macrocells, and four global output enables
for devices with 144 or more macrocells. Any selected out-
put enable signal may be inverted locally at each pin output
to provide maximal design flexibility.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as addi-
tional ground pins in order to force otherwise unused pins
to a low voltage state, as well as provide for additional
device grounding capability. This grounding of the pin is
achieved by internal logic that forces a logic low output
regardless of the internal macrocell signal, so the internal
macrocell logic is unaffected by the programmable ground
pin capability.
Each IOB also provides for bus-hold circuitry (also called a
“keeper”)that is active during valid user operation. The
bus-hold feature eliminates the need to tie unused pins
either high or low by holding the last known state of the
input until the next input signal is present. The bus-hold cir-
cuit drives back the same state via a nominal resistance
(R
BH
) of 50k ohms. See
Figure 13
. Note the bus-hold out-
put will drive no higher than V
CCIO
to prevent overdriving
signals when interfacing to 2.5V components.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50k ohm pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1k ohm) may be externally
added to any pin to override the default R
BH
resistance to
force a low state during power-up or any of these other
modes.
Figure 11: XC9500XL Devices in (a) 3.3V only and (b) Mixed 5V/3.3V/2.5V Systems
5V Tolerant I/Os
The I/Os on each XC9500XL device are fully 5V tolerant
even though the core power supply is 3.3 volts. This allows
5V CMOS signals to connect directly to the XC9500XL
inputs without damage. In addition, the 3.3V V
CCINT
power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V
CCINT
), and the output power sup-
ply (V
CCIO
) may have power applied in any order. This
makes the XC9500XL devices immune to power supply
sequencing problems.
Xilinx proprietary ESD circuitry and high impedance initial
state permit hot plugging cards using these devices.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design iteration depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500XL
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the
same pinout.
The XC9500XL architecture provides for superior pin-lock-
ing characteristics with a combination of large number of
IN
OUT
XCPLD
V
CCINT
V
CCIO
3.3 V
5 V CMOS
5 V
or
0 V
GND
(b)
X5901_01
5 V TTL
3.6 V
0 V
or
3.3 V CMOS
3.3 V
0 V
2.5 V CMOS
2.5 V
0 V
IN
OUT
XCPLD
V
CCINT
V
CCIO
3.3 V
5 V CMOS
5 V
or
or
0 V
GND
(a)
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
3.3 V CMOS, 5 V TTL
3.3 V
0 V
CMOS
2.5 V
0 V
2.5 V
2.5V CMOS
2.5 V
0 V
2.5V CMOS
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