![](http://datasheet.mmic.net.cn/Freescale-Semiconductor/MC68HC912B32CFU8_datasheet_98749/MC68HC912B32CFU8_318.png)
Electrical Specifications
M68HC12B Family Data Sheet, Rev. 9.1
318
Freescale Semiconductor
Figure 19-4. VFP Tracking VDD during Power-Down
When checking to ensure that the reservoir capacitance value of C4 is not too low, the voltage level of
VFP can be monitored during an initial erase and a write pulse. Remember that the largest current draw
on erasing is when all of the bits of the FLASH are programmed to 0. Conversely, the highest
programming current is seen when programming all the bits to 0 from the erased state of 1. The user
should look at this on an oscilloscope, due to the brevity of the pulses. Using a port pin or the SHDN signal
may be useful to trigger the scope when the pulses are fired. If the voltage dips below 11.4 volts, the
capacitance used can be increased, but be sure to verify that decay rates of VDD and VFP are still the
same. If VFP is declining with each successive pulse, try inserting some delays between each pulse to
allow the charge pump to recharge.
The solution shown here uses the ST662A dc-dc converter, but any similar device will work. Some other
options are the LTC1262C from Linear Technology Corporation or the MAX662 from Maxim Integrated
Products, Inc.