參數(shù)資料
型號(hào)： XC3S500E-5FGG320C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 29/227頁(yè)
文件大小： 0K
描述： IC FPGA SPARTAN-3E 500K 320-FBGA
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3E
LAB/CLB數(shù)： 1164
邏輯元件/單元數(shù)： 10476
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 232
門數(shù)： 500000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 320-BGA
供應(yīng)商設(shè)備封裝： 320-FBGA（19x19）
配用： 122-1536-ND - KIT STARTER SPARTAN-3E
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Spartan-3E FPGA Family: DC and Switching Characteristics
DS312 (v4.1) July 19, 2013
Product Specification
124
Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: -4 and the
higher performance -5. Switching characteristics in this
document may be designated as Advance, Preliminary, or
Production, as shown in Table 84. Each category is defined
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGAs designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx
ISE software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3E devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
Sign Up for Alerts on Xilinx.com
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3E speed files (v1.27), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for
these files are shown in Table 84. For more complete, more
precise, and worst-case data, use the values reported by
the Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Table 85 provides the history of the Spartan-3E speed files
since all devices reached Production status.
Table 84: Spartan-3E v1.27 Speed Grade Designations
Device
Advance
Preliminary
Production
XC3S100E
-MIN, -4, -5
XC3S250E
-MIN, -4, -5
XC3S500E
-MIN, -4, -5
XC3S1200E
-MIN, -4, -5
XC3S1600E
-MIN, -4, -5
Table 85: Spartan-3E Speed File Version History
Version
ISE
Release
Description
1.27
9.2.03i
Added XA Automotive.
1.26
8.2.02i
Added -0/-MIN speed grade, which
includes minimum values.
1.25
8.2.01i
Added XA Automotive devices to speed
file. Improved model for left and right
DCMs.
1.23
8.2i
Updated input setup/hold values based
on default IFD_DELAY_VALUE
settings.
1.21
8.1.03i
All Spartan-3E FPGAs and all speed
grades elevated to Production status.
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