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參數(shù)資料
| 型號(hào)： | XC3S250E-4CPG132I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 11/227頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 250K 132CSBGA |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 612 |
| 邏輯元件/單元數(shù)： | 5508 |
| RAM 位總計(jì)： | 221184 |
| 輸入/輸出數(shù)： | 92 |
| 門數(shù)： | 250000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 132-TFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 132-CSPBGA（8x8） |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
108
Bitstream Generator (BitGen) Options
For additional information, refer to the “Configuration
Bitstream Generator (BitGen) Settings” chapter in UG332.
Various Spartan-3E FPGA functions are controlled by
specific bits in the configuration bitstream image. These
values are specified when creating the bitstream image with
the Bitstream Generator (BitGen) software.
Table 69 provides a list of all BitGen options for Spartan-3E
FPGAs.
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Option Name
Pins/Function
Affected
Values
(default)
Description
ConfigRate
CCLK,
Configuration
1, 3, 6,
12, 25, 50
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency, and the new setting is loaded as part of the configuration bitstream. The
software default value is 1 (~1.5 MHz) starting with ISE 8.1, Service Pack 1.
StartupClk
Configuration,
Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
UserClk
A clock signal from within the FPGA application controls the startup sequence when the
FPGA transitions from configuration mode to the user mode. See Start-Up. The FPGA
application supplies the user clock on the CLK pin on the STARTUP_SPARTAN3E
primitive.
Jtag
The JTAG TCK input controls the startup sequence when the FPGA transitions from the
configuration mode to the user mode. See Start-Up.
UnusedPin
Unused I/O
Pins
Pulldown
Default. All unused I/O pins and input-only pins have a pull-down resistor to GND.
Pullup
All unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply
for its associated I/O bank.
Pullnone
All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance,
three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal
level.
DONE_cycle
DONE pin,
Configuration
Startup
1, 2, 3, 4,
5, 6
Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
GWE_cycle
All flip-flops,
LUT RAMs, and
SRL16 shift
registers, Block
RAM,
Configuration
Startup
1, 2, 3, 4,
5, 6
Selects the Configuration Startup phase that asserts the internal write-enable signal to
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read and
write operations. See Start-Up.
Done
Waits for the DONE pin input to go High before asserting the internal write-enable signal
to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and write
operations are enabled at this time.
Keep
Retains the current GWE_cycle setting for partial reconfiguration applications.
GTS_cycle
All I/O pins,
Configuration
1, 2, 3, 4,
5, 6
Selects the Configuration Startup phase that releases the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up.
Done
Waits for the DONE pin input to go High before releasing the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point.
Keep
Retains the current GTS_cycle setting for partial reconfiguration applications.
LCK_cycle
DCMs,
Configuration
Startup
NoWait
The FPGA does not wait for selected DCMs to lock before completing configuration.
0, 1, 2, 3,
4, 5, 6
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE, the
FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
DonePin
DONE pin
Pullup
Internally connects a pull-up resistor between DONE pin and VCCAUX. An external
330
Ω pull-up resistor to VCCAUX is still recommended.
Pullnone
No internal pull-up resistor on DONE pin. An external 330
Ω pull-up resistor to VCCAUX
is required.
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