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參數(shù)資料
| 型號(hào)： | XC3S1500-5FGG676C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 219/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1.5M 676-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 3328 |
| 邏輯元件/單元數(shù)： | 29952 |
| RAM 位總計(jì)： | 589824 |
| 輸入/輸出數(shù)： | 487 |
| 門數(shù)： | 1500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
| 配用： | NANO-SPARTAN-ND - KIT NANOBOARD AND SPARTAN3 DC 807-1001-ND - DAUGHTER CARD XILINX SPARTAN 3 |
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Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
50
Master Parallel Mode
In this mode, the FPGA configures from byte-wide data, and the FPGA supplies the CCLK configuration clock. In Master
configuration modes, CCLK behaves as a bidirectional I/O pin. Timing is similar to the Slave Parallel mode except that CCLK
is supplied by the FPGA. The device connections are shown in Figure 28.
Boundary-Scan (JTAG) Mode
In Boundary-Scan mode, dedicated pins are used for configuring the FPGA. The configuration is done entirely through the
IEEE 1149.1 Test Access Port (TAP). FPGA configuration using the Boundary-Scan mode is compatible with the IEEE Std
1149.1-1993 standard and IEEE Std 1532 for In-System Configurable (ISC) devices.
Configuration through the boundary-scan port is always available, regardless of the selected configuration mode. In some
cases, however, the mode pin setting may affect proper programming of the device due to various interactions. For example,
if the mode pins are set to Master Serial or Master Parallel mode, and the associated PROM is already programmed with a
valid configuration image, then there is potential for configuration interference between the JTAG and PROM data. Selecting
the Boundary-Scan mode disables the other modes and is the most reliable mode when programming via JTAG.
Configuration Sequence
The configuration of Spartan-3 devices is a three-stage process that occurs after Power-On Reset or the assertion of
PROG_B. POR occurs after the VCCINT, VCCAUX, and VCCO Bank 4 supplies have reached their respective maximum input
threshold levels (see Table 29, page 59). After POR, the three-stage process begins.
First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is
activated by a start-up process. A flow diagram for the configuration sequence of the Serial and Parallel modes is shown in
Figure 29. The flow diagram for the Boundary-Scan configuration sequence appears in Figure 30.
X-Ref Target - Figure 28
Figure 28: Connection Diagram for Master Parallel Configuration
Spartan-3
Master
D[0:7]
CCLK
PROG_B
DONE
INIT_B
DATA[0:7]
CCLK
RDWR_B
CS_B
CF
CE
OE/RESET
Platform Flash
PROM
DS099_25_112905
2.5V
VCCAUX
VCCO Banks 4 & 5
VCCINT
1.2V
GND
1.8V
VCCINT
VCCJ
VCCO
2.5V
XCFxxP
2.5V
All
4.7K
Ω
Notes:
1.
There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for
the last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This
enables the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the
remaining FPGAs in the chain. Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines
are open-drain and require the pull-up resistor shown in grey. In most cases, a value between 3.3K
Ω to
4.7K
Ω is sufficient. However, when using DONE synchronously with a long chain of FPGAs, cumulative
capacitance may necessitate lower resistor values (e.g. down to 330
Ω) in order to ensure a rise time within
one clock cycle.
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