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參數(shù)資料
| 型號(hào)： | XC3S1500-5FGG676C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 196/272頁(yè) |
| 文件大小： | 0K |
| 描述： | SPARTAN-3A FPGA 1.5M 676-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 3328 |
| 邏輯元件/單元數(shù)： | 29952 |
| RAM 位總計(jì)： | 589824 |
| 輸入/輸出數(shù)： | 487 |
| 門數(shù)： | 1500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
| 配用： | NANO-SPARTAN-ND - KIT NANOBOARD AND SPARTAN3 DC 807-1001-ND - DAUGHTER CARD XILINX SPARTAN 3 |
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Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
Product Specification
3
Architectural Overview
The Spartan-3 family architecture consists of five fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical
functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB
supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight
high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are
included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board
designs.
Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying,
dividing, and phase shifting clock signals.
These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a
single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several
18-Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer
block RAM columns.
The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements,
transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections
to the routing.
Configuration
Spartan-3 FPGAs are programmed by loading configuration data into robust reprogrammable static CMOS configuration
latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA,
configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying
X-Ref Target - Figure 1
Figure 1: Spartan-3 Family Architecture
DS099-1_01_032703
Notes:
1.
The two additional block RAM columns of the XC3S4000 and XC3S5000 devices
are shown with dashed lines. The XC3S50 has only the block RAM column on the
far left.
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