參數資料
型號: XC3S1400A-4FT256I
廠商: Xilinx Inc
文件頁數: 20/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 256FTBGA
標準包裝: 90
系列: Spartan®-3A
LAB/CLB數: 2816
邏輯元件/單元數: 25344
RAM 位總計: 589824
輸入/輸出數: 161
門數: 1400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應商設備封裝: 256-FTBGA
Pinout Descriptions
116
DS529-4 (v2.0) August 19, 2010
User I/Os by Bank
Table 84 and Table 85 indicate how the user-I/O pins are
distributed between the four I/O banks on the FG484
package. The AWAKE pin is counted as a dual-purpose I/O.
Footprint Migration Differences
Table 86 summarizes any footprint and functionality
differences between the XC3S700A and the XC3S1400A
FPGAs that might affect easy migration between devices
available in the FG484 package. There are three such balls.
All other pins not listed in Table 86 unconditionally migrate
between Spartan-3A devices available in the FG484
package.
The arrows indicate the direction for easy migration.
Table 84: User I/Os Per Bank for the XC3S700A in the FG484 Package
Package
Edge
I/O Bank
Maximum I/O
All Possible I/O Pins by Type
I/O
INPUT
DUAL
VREF
CLK
Top
0
92
58
17
1
8
Right
1
94
33
15
30
8
Bottom
2
92
43
11
21
9
8
Left
3
94
61
17
0
8
TOTAL
372
195
60
52
33
32
Table 85: User I/Os Per Bank for the XC3S1400A in the FG484 Package
Package
Edge
I/O Bank
Maximum I/O
All Possible I/O Pins by Type
I/O
INPUT
DUAL
VREF
CLK
Top
0
92
58
17
1
8
Right
1
94
33
15
30
8
Bottom
2
95
43
13
21
10
8
Left
3
94
61
17
0
8
TOTAL
375
195
62
52
34
32
Table 86: FG484 Footprint Migration Differences
Pin
Bank
XC3S700A
Migration
XC3S1400A
T8
2
N.C.
INPUT/VREF
U7
2
N.C.
INPUT
U16
2
N.C.
INPUT
DIFFERENCES
3
Legend:
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
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