參數(shù)資料
型號: XC3S1400A-4FT256I
廠商: Xilinx Inc
文件頁數(shù): 103/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 2816
邏輯元件/單元數(shù): 25344
RAM 位總計: 589824
輸入/輸出數(shù): 161
門數(shù): 1400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Pinout Descriptions
72
DS529-4 (v2.0) August 19, 2010
User I/Os by Bank
Table 64 indicates how the 68 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.
Footprint Migration Differences
The XC3S50A and XC3S200 have common VQ100 pinouts
except for some differences in alignment of differential I/O
pairs.
Differential I/O Alignment Differences
Some differential I/O pairs in the VQ100 on the XC3S50A
FPGA are aligned differently than the corresponding pairs
on the XC3S200A FPGAs, as shown in Table 65. All the
mismatched pairs are in I/O Bank 2. These differences are
indicated with the black diamond character (
) in the
footprint diagrams Figure 17 and Figure 18.
Table 64: User I/Os Per Bank for the XC3S50A and XC3S200A in the VQ100 Package
Package
Edge
I/O Bank
Maximum I/O
All Possible I/O Pins by Type
I/O
INPUT
DUAL
VREF
CLK
Top
0
15
3
1
3
7
Right
1
13
6
0
1
6
Bottom
2
26
2
0
19
1
4
Left
3
14
6
1
0
1
6
TOTAL
68
17
2
20
6
23
Table 65: Differential I/O Differences in VQ100
VQ100 Pin
Bank
XC3S50A
XC3S200A
P29
2
IIO_L04P_2/VS2
IO_L03N_2/VS2
P30
IO_L03N_2/VS1
IO_L04P_2/VS1
P33
IO_L06P_2
IO_L05N_2
P34
IO_L05N_2/D7
IO_L06P_2/D7
P51
IO_L11N_2/D0/DIN/
MISO
IO_L12P_2/D0/DIN/
MISO
P52
IO_L12P_2/D1
IO_L11N_2/D1
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