參數(shù)資料
型號(hào): XC3S1400A-4FT256I
廠商: Xilinx Inc
文件頁數(shù): 132/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 2816
邏輯元件/單元數(shù): 25344
RAM 位總計(jì): 589824
輸入/輸出數(shù): 161
門數(shù): 1400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Pinout Descriptions
DS529-4 (v2.0) August 19, 2010
99
User I/Os by Bank
Table 78 and Table 79 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package. The AWAKE pin is counted as a
dual-purpose I/O.
Footprint Migration Differences
Table 80 summarizes any footprint and functionality
differences between the XC3S200A and the XC3S400A
FPGAs that might affect easy migration between devices
available in the FG320 package. There are three such balls.
All other pins not listed in Table 80 unconditionally migrate
between Spartan-3A devices available in the FG320
package.
The arrows indicate the direction for easy migration.
Table 78: User I/Os Per Bank for XC3S200A in the FG320 Package
Package
Edge
I/O Bank
Maximum I/O
All Possible I/O Pins by Type
I/O
INPUT
DUAL
VREF
CLK
Top
0
60
35
11
1
5
8
Right
1
64
9
10
30
7
8
Bottom
2
60
19
6
21
6
8
Left
3
64
38
13
0
5
8
TOTAL
248
101
40
52
23
32
Table 79: User I/Os Per Bank for XC3S400A in the FG320 Package
Package
Edge
I/O Bank
Maximum I/O
All Possible I/O Pins by Type
I/O
INPUT
DUAL
VREF
CLK
Top
0
61
35
12
1
5
8
Right
1
64
9
10
30
7
8
Bottom
2
62
19
7
21
7
8
Left
3
64
38
13
0
5
8
TOTAL
251
101
42
52
24
32
Table 80: FG320 Footprint Migration Differences
Pin
Bank
XC3S200A
Migration
XC3S400A
E13
0
N.C.
INPUT
N7
2
N.C.
INPUT
P14
2
N.C.
INPUT/VREF
DIFFERENCES
3
Legend:
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
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