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參數(shù)資料
| 型號： | XA-H3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS 16-bit highly integrated microcontroller |
| 中文描述： | 的CMOS 16位高度集成的微控制器 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XA-H3 |
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Philips Semiconductors
Preliminary specification
XA-H3
CMOS 16-bit highly integrated microcontroller
1999 Sep 24
17
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write or
Read Only
Memory Interface (MIF) Registers
B0CFG
R/W
8
280h
MIF Bank 0 Config
0Fh
B0AM
R/W
8
281h
MIF Bank 0 Base Address
00h
B0TMG
R/W
8
282h
MIF Bank 0 Timing Params
B1CFG
R/W
8
284h
MIF Bank 1 Config
B1AM
R/W
8
285h
MIF Bank 1 Base Address
B1TMG
R/W
8
286h
MIF Bank 1 Timing Params
B2CFG
R/W
8
288h
MIF Bank 2 Config
B2AM
R/W
8
289h
MIF Bank 2 Base Address
B2TMG
R/W
8
28Ah
MIF Bank 2 Timing Params
B3CFG
R/W
8
28Ch
MIF Bank 3 Config
B3AM
R/W
8
28Dh
MIF Bank 3 Base Address
B3TMG
R/W
8
28Eh
MIF Bank 3 Timing Params
B4CFG
R/W
8
290h
MIF Bank 4 Config
B4AM
R/W
8
291h
MIF Bank 4 Base Address
B4TMG
R/W
8
292h
MIF Bank 4 Timing Params
B5CFG
R/W
8
294h
MIF Bank 5 Config
B5AM
R/W
8
295h
MIF Bank 5 Base Address
B5TMG
R/W
8
296h
MIF Bank 5 Timing Params
MBCL
R/W
8
2BEh
MIF Memory Bank Configuration Lock Register
Reserved – do not write
R/W
8
2BFh
Reserved – do not write
Miscellaneous Registers
Hi-Pri Soft Ints & Pin Mux Control Reg.
R/W
16
2D0h
Control bits for Hi-Priority Soft Ints, and Pin Mux
0000h
XInt2
R/W
8
2D2h
External Interrupt 2 Control
00h
FUNCTIONAL DESCRIPTION
The XA-H3 functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook or the XA-H3 User Manual only brief descriptions
are given in this datasheet, in conjunction with references to the
appropriate document.
XA CPU
The CPU is a 30 MHz implementation of the standard XA CPU core.
See the XA Data Handbook(IC25) for details. The CPU core is
identical to the G3 core. See caveat in next paragraph about the Bus
Interface Unit.
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to Memory Controller.
WARNING:
Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register, it comes out of reset
initialized to 07h, which is the only value that will work.
XA CPU
Memory
Controller
BIU
DMA
Channels
x8
External
Memory
and I/O Bus
SU01236
Internal Cpu Bus
Figure 1. XA CPU Core BIU (Bus Interface Unit)
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