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參數(shù)資料
| 型號： | XA-H3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS 16-bit highly integrated microcontroller |
| 中文描述： | 的CMOS 16位高度集成的微控制器 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XA-H3 |
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Philips Semiconductors
Preliminary specification
XA-H3
CMOS 16-bit highly integrated microcontroller
1999 Sep 24
11
Name
Reset
Value
Bit Functions and Addresses
MSB
LSB
SFR
Address
Description
28F
28E
28D
28C
28B
28A
289
288
TSTAT*
Timer 0/1 Extended Status
411h
–
–
–
–
–
T1OE
–
T0OE
00h
2FF
2FE
2FD
2FC
2FB
2FA
2F9
2F8
WDCON*
Watchdog Control
41Fh
PRE2
PRE1
PRE0
–
–
WDRUN
WDTOF
–
6
WDL
Watchdog Timer Reload
45Fh
00h
WFEED1
Watchdog Feed 1
45Dh
x
WFEED2
NOTES:
*
SFRs marked with an asterisk (*) are bit addressable.
#
SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4.
1. The XA-H3 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide All SFR accesses must be
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the
upper byte.
2. SFR is loaded from the reset vector.
3. F1, F0, and P reset to “0”. All other bits are loaded from the reset vector.
4. Unimplemented bits in SFRs are “X” (unknown) at all times. “1”s should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is “0”.
5. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and
PnCFGB register will contain 00h. See warning in XA-H3 User Manualabout P3.2_Timer0_ResetOut pin during first 258 clocks after power
up. Basically, during this period, this pin may output a strongly-driven low pulse. If the pulse does occur, it will terminate in a transition to high
at a time no later than the 259th system clock after valid V
power up.
6. The WDCON reset value is E6 for a Watchdog reset; E4 for all other reset causes.
7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to “1”, the others will be “0”. RSTSRC[7] enables the ResetOut
function; “1” = Enabled, “0” = Disabled. See XA-H3 User Manualfor details; RSTSRC[7] differs in function from most other XA derivatives.
8. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or
other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write
operation. XA-H3 SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON).
Watchdog Feed 2
45Eh
x
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