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參數(shù)資料
| 型號(hào)： | X80130 |
| 英文描述： | Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors(帶當(dāng)?shù)?遠(yuǎn)程電壓監(jiān)控功能的電源順序管理器) |
| 中文描述： | 電壓監(jiān)控器/可編程序三時(shí)滯與本地/遠(yuǎn)程電壓監(jiān)測(cè)器（帶當(dāng)?shù)?遠(yuǎn)程電壓監(jiān)控功能的電源順序管理器） |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 104K |
| 代理商： | X80130 |
REV 1.13 4/30/03
www.xicor.com
Characteristics subject to change without notice
9 of 19
X80130/31/32/33/34 – Preliminary Information
DESCRIPTION
The X80130 is a voltage supervisor/sequencer with three built in
voltage monitors. This allows the designer to monitor up to three
voltages and sequence up to four events.
Low voltage detection circuitry protects the system from power
supply failure or “brown out” conditions, resetting the system and
resequencing the voltages when any of the monitored inputs fall
below the minimum threshold level. The RESET pin is active
until all monitored voltages reach proper operating levels and
stabilize for a selectable period of time. Five common low volt-
age combinations are available, however, Xicor’s unique circuits
allow the any voltage monitor threshold to be reprogrammed for
special needs or for applications requiring higher precision.
A manual reset input provides debounce circuitry for minimum
reset component count. Activating the manual reset both con-
trols the RESET output and resequences the supplies through
control of the ViFAIL pins.
The X80130 has 2kb of EEPROM for system configuration,
manufacturing or maintenance information. This memory is pro-
tected to prevent inadvertent changes to the contents.
FUNCTIONAL DESCRIPTION
Power On Reset and System Reset With Delay
Application of power to the X80130 activates a Power On Reset
circuit that pulls the RESET pin active. This signal, if used,
prevents the system microprocessor from starting to operate
while there is insufficient voltage on any of the supplies. This
circuit also does the following:
– It prevents the processor from operating prior to
stabilization of the oscillator.
– It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
– It prevents communication to the EEPROM during unstable
power conditions, greatly reducing the likelihood of data
corruption on power up.
– It allows time for all supplies to turn on and stabilize prior to
system initialization.
The POR/RESET circuit is activatived when all voltages are
within specified ranges and the V1GDO, V3GDO, and V4GDO
time-out conditions are met. The POR/RESET circuit will then
wait t
SPOR
and de-assert the RESET pin. The POR delay may
be changed by setting the TPOR bits in register CR2. The delay
can be set to 100 ms, 500 ms, 1 second, or 5 seconds.
Table 1.
POR RESET Delay Options
Manual Reset
The manual reset option allows a hardware reset of the power
sequencing pins. These can be used to recover the system in
the event of an abnormal operating condition. Activating the MR
pin for more than 5
μ
s sets all of the ViFAIL outputs and the
RESET output active (LOW). When MR is released (and if all
supplies are still at their proper operating voltage) then the
ViFAIL and RESET pins will be released after their programmed
delay periods. (See
Triple Voltage Monitoring
X80130 monitors 3 voltage inputs. When the ViMON (i =1, 3, 4)
input is detected to be above the input threshold, the output
ViFAIL (i =1, 3, 4) goes inactive (LOW). The ViFAIL signal is de-
asserted after a delay of 100ms. This delay can be changed on
each ViFAIL output individually with bits in register CR3. The
delay can be 100ms, 500ms, 1s and 5s. Each ViFAIL signal
remains active until its associated ViMON input rises above the
threshold.
Table 2.
ViFAIL output Time Delay Options
Fault Detection
The X80130 contains a Fault Detection Register (FDR) that
provides the user the status of the causes for a RESET pin
active (See Table 20).
At power-up, the FDR is defaulted to all “0”. The system needs to
initialize the register to all “1” before the actual monitoring can
take place. In the event that any one of the monitored sources
fail, the corresponding bit in the register changes from a “1” to a
“0” to indicate the failure. When a RESET is detected by the
main controller, the controller should read the FDR and note the
cause of the fault. After reading the register, the controller can
reset the register bit back to all “1” in preparation for future failure
conditions.
Flexible Power Sequencing of Multiple Power Supplies
The X80130 provides several circuits such as multiple voltage
monitors, programmable delays, and output drive signals that
can be used to set up flexible power monitoring or sequencing
schemes system power supplies. Below are two examples:
1)
Power Up of Supplies In Parallel Using Programmable
Delays. (See Figure 7 and Figure 8).
The X80130 monitors several power supplies, powered by
the same source voltage, that all begin power up at the
same time. Each voltage source is fed into the ViMON
TPOR1
0
0
1
1
TPOR0
0
1
0
1
t
SPOR
delay before RESET assertion
100 miliseconds (default)
500 miliseconds
1 second
5 seconds
TiD1
0
0
1
1
where i is the specific voltage monitor (i = 1, 3, 4).
TiD0
0
1
0
1
t
DELAYi
100ms (default)
500ms
1 secs
5 secs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X80130Q20I | 制造商:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80131 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80131Q20I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80132 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80132Q20I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
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