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參數(shù)資料
| 型號： | X80130 |
| 英文描述： | Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors(帶當?shù)?遠程電壓監(jiān)控功能的電源順序管理器) |
| 中文描述： | 電壓監(jiān)控器/可編程序三時滯與本地/遠程電壓監(jiān)測器（帶當?shù)?遠程電壓監(jiān)控功能的電源順序管理器） |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 104K |
| 代理商： | X80130 |
REV 1.13 4/30/03
www.xicor.com
Characteristics subject to change without notice
15 of 19
X80130/31/32/33/34 – Preliminary Information
– The next bit, SA1, selects the device memory sector. There
are two addressable sectors: the memory array and the
control, fault detection and remote shutdown registers.
– The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be per-
formed. When the R/W bit is “1”, then a READ operation is
selected. A “0” selects a WRITE operation (Refer toFigure
13).
Figure 13. Slave Address Format
Serial Write Operations
Before any write operations can be performed, a programming
supply voltage (V
P
) must be supplied. This voltage is only
needed for programming, but the nonvolatile registers and
EEPROM locations cannot be programmed without it.
In order to successfully complete a write operation to either a
Control Register or the EEPROM array, the Write Enable Latch
(WEL) bit must first be set and either the WP pin or the WPEN
bit must be LOW.
Writes to the WEL bit do not cause a high voltage write cycle, so
the device is ready for the next operation immediately after the
stop condition.
B
YTE
W
RITE
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master access to
any one of the words in the array. After receipt of the Word
Address Byte, the device responds with an acknowledge, and
awaits the next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an acknowledge. The
master then terminates the transfer by generating a stop
condition, at which time the device begins the internal write cycle
to the nonvolatile memory. During this internal write cycle, the
device inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high impedance.
A write to a protected block of memory will suppress the
acknowledge bit.
P
AGE
W
RITE
The device is capable of a page write operation. See Figure 14.
It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data byte is
transferred, the master can transmit an unlimited number of 8-bit
bytes. After the receipt of each byte, the device will respond with
an acknowledge, and the address is internally incremented by
one. The page address remains constant. When the counter
reaches the end of the page, it “rolls over” and goes back to ‘0’
on the same page. See Figure 15.
This means that the master can write 16 bytes to the page
starting at any location on that page. If the master begins writing
at location 10, and loads 12 bytes, then the first 6 bytes are
written to locations 10 through 15, and the last 6 bytes are
written to locations 0 through 5. Afterwards, the address counter
would point to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time.
The master terminates the Data Byte loading by issuing a stop
condition, which causes the device to begin the nonvolatile write
cycle. As with the byte write operation, all inputs are disabled
until completion of the internal write cycle.
S
TOPS
AND
W
RITE
M
ODES
Stop conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte plus the
subsequent ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte plus its associated ACK is
sent, then the device will reset itself without performing the write.
The contents of the array will not be effected.
A
CKNOWLEDGE
P
OLLING
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time. Once
the stop condition is issued to indicate the end of the master’s
byte load operation, the device initiates the internal high voltage
cycle. Acknowledge polling can be initiated immediately. To do
this, the master issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device is still
busy with the high voltage cycle then no ACK will be returned. If
the device has completed the write operation, an ACK will be
returned and the host can then proceed with the read or write
operation. See Figure 18.
SA6
SA7
SA5
SA3
SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ /
WRITE
SA4
R/W
1
0
1
0
ADDRESS
EXTERNAL
DEVICE
Memory
Select
A1
A0
MS
Internal
Address
(SA1)
0
1
Internally Addressed
Device
EEPROM Array
Control Register,
Fault Detection Register
Bit SA0
0
1
Operation
WRITE
READ
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相關(guān)代理商/技術(shù)參數(shù) |
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| X80130Q20I | 制造商:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80131 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80131Q20I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80132 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80132Q20I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
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