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參數(shù)資料
| 型號： | X80130 |
| 英文描述： | Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors(帶當?shù)?遠程電壓監(jiān)控功能的電源順序管理器) |
| 中文描述： | 電壓監(jiān)控器/可編程序三時滯與本地/遠程電壓監(jiān)測器（帶當?shù)?遠程電壓監(jiān)控功能的電源順序管理器） |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 104K |
| 代理商： | X80130 |
REV 1.13 4/30/03
www.xicor.com
Characteristics subject to change without notice
14 of 19
X80130/31/32/33/34 – Preliminary Information
BUS INTERFACE INFORMATION
Interface Conventions
The device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter, and the receiving device as the receiver. The device
controlling the transfer is called the master and the device being
controlled is called the slave. The master always initiates data
transfers, and provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate as
slaves in all applications.
It should be noted that the ninth clock cycle of the read operation
is not a “don’t care.” To terminate a read operation, the master
must either issue a stop condition during the ninth cycle or hold
SDA HIGH during the ninth clock cycle and then issue a stop
condition.
Serial Clock and Data
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. See Figure 11.
Serial Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The device
continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this
condition has been met.
Serial Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is HIGH.
The stop condition is also used to place the device into the
Standby power mode after a read sequence. A stop condition
can only be issued after the transmitting device has released the
bus.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either master
or slave, will release the bus after transmitting eight bits. During
the ninth clock cycle, the receiver will pull the SDA line LOW to
acknowledge that it received the eight bits of data. See Figure
12.
The device will respond with an acknowledge after recognition of
a start condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write operation
is selected, the device will respond with an acknowledge after
the receipt of each subsequent eight bit word. The device will
acknowledge all incoming data and address bytes, except for
the Slave Address Byte when the Device Identifier and/or Select
bits are incorrect.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an acknowledge. If
an acknowledge is detected and no stop condition is generated
by the master, the device will continue to transmit data. The
device will terminate further data transmissions if an
acknowledge is not detected. The master must then issue a stop
condition to return the device to Standby mode and place the
device into a known state.
Figure 11. Valid Start and Stop Conditions
Figure 12. Acknowledge Response From Receiver
DEVICE ADDRESSING
Addressing Protocol Overview
Depending upon the operation to be performed on each of these
individual parts, a 1, 2 or 3 Byte protocol is used. All operations
however must begin with the Slave Address Byte being clocked
into the SMBus port on the SCL and SDA pins. The Slave
address selects the part of the device to be addressed, and
specifies if a Read or Write operation is to be performed.
Slave Address Byte
Following a START condition, the master must output a Slave
Address Byte. This byte consists of three parts:
– The Device Type Identifier which consists of the most sig-
nificant four bits of the Slave Address (SA7 - SA4). The
Device Type Identifier MUST be set to 1010 in order to
select the device.
– The next two bits (SA3 - SA2) are slave address bits. The
bits received via the SMBus are compared to A0 and A1
pins and must match or the communication is aborted.
SCL
SDA
Start
Stop
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
SCL from
Master
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X80130Q20I | 制造商:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80131 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80131Q20I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80132 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
| X80132Q20I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors |
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