REV 1.13 4/30/03
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Characteristics subject to change without notice
8 of 19
X80130/31/32/33/34 – Preliminary Information
PIN OUTS
PIN DESCRIPTIONS
Pin
1
Name
V4GDO
V4 Voltage Good Delay Output (Active
LOW).
This open drain output goes HIGH
when V4MON is less than V
REF4
and goes
LOW when V4MON is greater than V
REF4
.
There is user selectable delay circuitry on
this pin.
V4MON
V4 Voltage Monitor Input.
Third voltage
monitor pin. If unused connect to V
CC
.
V3GDO
V3 Voltage Good Delay Output (Active
LOW).
This open drain output goes HIGH
when V3MON is less than V
REF3
and goes
LOW when V3MON is greater than V
REF3
.
There is user selectable delay circuitry on
this pin.
V3MON
V3 Voltage Monitor Input.
Second voltage
monitor pin. If unused connect to V
CC
.
DNC
Do Not Connect
V
P
EEPROM programming Voltage.
V
CC
Connect to V
CC
.
DNC
Do Not Connect.
A1
Address Select Input. It has an internal
pull-down resistor. (>10M
typical)
The A0 and A1 bits allow for up to 4 X80130
devices to be used on the same SMBus
serial interface.
SDA
Serial Data.
SDA is a bidirectional pin used
to transfer data into and out of the device.
It has an open drain output and may be wire
ORed with other open drain or open collec-
tor outputs. This pin requires a pull up resis-
tor and the input buffer is always active (not
gated).
Description
2
3
4
5
6
7
8
9
10
QFN package
(Top view)
V1GDO
V1MON
M
N
V3GDO
V3MON
DNC
V4MON
RESET
WP
V4GDO
SCL
1
2
3
4
5
6
7
18
19
20
V
C
8
17
(5mm x 5mm)
9 10
11
V
P
12
14
13
15
16
A
D
A
S
V
C
V
S
11
SCL
Serial Clock.
The Serial Clock controls the
serial bus timing for data input and output.
V1MON
V1 Voltage Monitor Input.
First voltage
monitor pin. If unused connect to V
CC
.
V1GDO
V1 Voltage Good Delay Output (Active
LOW).
This open drain output goes HIGH
when V1MON is less than V
REF1
and goes
LOW when V1MON is greater than V
REF1
.
There is user selectable delay circuitry on
this pin.
RESET
RESET Output.
This open drain pin is an
active LOW output. This pin will be active
until all ViGDO pins go inactive and the
power sequencing is complete. This pin will
be released after a programmable delay.
WP
Write Protect. Input Pin.
WP HIGH (in
conjunction with WPEN bit=1) prevents
writes to any memory location in the device.
It has an internal pull-down resistor.
(>10M
typical)
MR
Manual Reset.
Pulling the MR pin HIGH
initiates a RESET. The MR signal must be
held HIGH for 5
μ
secs. It has an internal
pull-down resistor. (>10M
typical)
V
SS
Ground Input.
NC
No Connect.
No internal connections.
A0
Address Select Input.
It has an internal
pull-down resistor. (>10M
typical)
The A0 and A1 bits allow for up to 4 X80130
devices to be used on the same SMBus
serial interface.
V
CC
Supply Voltage.
12
13
14
15
16
17
18
19
20
Pin
Name
Description