參數(shù)資料
型號(hào): X80130
英文描述: Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors(帶當(dāng)?shù)?遠(yuǎn)程電壓監(jiān)控功能的電源順序管理器)
中文描述: 電壓監(jiān)控器/可編程序三時(shí)滯與本地/遠(yuǎn)程電壓監(jiān)測(cè)器(帶當(dāng)?shù)?遠(yuǎn)程電壓監(jiān)控功能的電源順序管理器)
文件頁(yè)數(shù): 17/19頁(yè)
文件大?。?/td> 104K
代理商: X80130
REV 1.13 4/30/03
www.xicor.com
Characteristics subject to change without notice
17 of 19
X80130/31/32/33/34 – Preliminary Information
Figure 18. Acknowledge Polling Sequence
Serial Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current Address Reads, Random Reads, and
Sequential Reads.
R
ANDOM
R
EAD
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave Address
Byte with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition
and the Slave Address Byte, receives an acknowledge, then
issues the Word Address Bytes. After acknowledging receipts of
the Word Address Bytes, the master immediately issues another
start condition and the Slave Address Byte with the R/W bit set
to one. This is followed by an acknowledge from the device and
then by the eight bit word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. See Figure 16 for the address,
acknowledge, and data transfer sequence.
C
URRENT
A
DDRESS
R
EAD
Internally the device contains an address counter that maintains
the address of the last word read incremented by one.
Therefore, if the last read was to address n, the next read
operation would access data from address n+1. On power up,
the address of the address counter is undefined, requiring a
read or write operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit set to
one, the device issues an acknowledge and then transmits the
eight bits of the Data Byte. The master terminates the read
operation when it does not respond with an acknowledge during
the ninth clock and then issues a stop condition. See Figure 17
or the address, acknowledge, and data transfer sequence.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible to
write to the device.
– SDA pin is the input mode.
Data Protection
The following circuitry has been included to prevent inadvertent
writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required prior
to the stop bit in order to start a nonvolatile write cycle.
– The WP pin, when held HIGH, prevents all writes to the
array and all the Register.
– A programming voltage must be applied to the V
P
pin prior
to any programming sequence.
ACK
Returned
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
Complete. Continue
Command Sequence
Issue STOP
NO
Continue Normal
Read or Write
Command Sequence
PROCEED
YES
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