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參數(shù)資料
| 型號(hào)： | X4C105V20-VTRIP |
| 元件分類： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 258K |
| 代理商： | X4C105V20-VTRIP |
REV 1.0.1 6/14/01
Characteristics subject to change without notice.
1 of 19
www.xicor.com
FEATURES
4Kbit serial EEPROM
—400kHz serial interface speed
—16-byte page write mode
One nibble NOVRAM
—120ns NOVRAM access speed
—AUTOSTORE
—Direct/bus access of NOVRAM bits
Four output ports
Operates at 3.3V ± 10%
Low voltage reset when V
—3% accurate thresholds available
—Output signal shows low voltage condition
—Activates NOVRAM AUTOSTORE
—Internal block on EEPROM operation
Max EEPROM/NOVRAM nonvolatile write cycle:
5ms
High reliability
—1,000,000 endurance cycles
—Guaranteed data retention: 100 years
20-lead TSSOP package
CC
< 3V
DESCRIPTION
The low voltage X4C105 combines several functions
into one device. The first is a 2-wire, 4Kbit serial
EEPROM memory with write protection. A Write Pro-
tect (WP) pin provides hardware protection for the
upper half of this memory against inadvertent writes.
A one nibble NOVRAM is provided and occupies a sin-
gle location. This allows access of 4-bits in a single
150ns cycle. This is useful for tracking system opera-
tion or process status. The NOVRAM memory is com-
pletely isolated from the serial memory section.
A low voltage detect circuit activates a RESET pin
when V
CC
drops below 3V. This signal also blocks new
read or write operations and initiates a NOVRAM
AUTOSTORE. The AUTOSTORE operation is pow-
ered by an external capacitor to ensure that the value
in the NOVRAM is always maintained in the event of a
power failure.
The four NOVRAM bits also appear on four separate
output pins to allow continuous control of external cir-
cuitry, such as ASICs.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Command
Decode
and
Control
Logic
HV Generation
Timing and Control
EEPROM
Array
X
Y Decoder
Data Register
Write Control Logic
WP
SCL
SDA
S1
S2
D0
D1
D2
D3
CE
OE
WE
I/O
Buffers
Control
Logic
and
Timing
Static RAM
Memory
4Kbits
EEPROM
Memory
V
CC
V
SS
RESET
Voltage
Monitor
Supply
Power On Reset
Low Voltage Detect
CAP
O0
O1
O2
O3
Output
Buffers
and
Latches
4K
X4C105
CPU Supervisor with NOVRAM and Output Ports
NOVRAM/EEPROM
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