參數(shù)資料
型號: X3100V28Z
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28
封裝: ROHS COMPLIANT, PLASTIC, MO-153AE, TSSOP-28
文件頁數(shù): 2/41頁
文件大?。?/td> 561K
代理商: X3100V28Z
10
FN8110.1
January 3, 2008
Cell Number Selection
The X3100 is designed to operate with four (4) Li-Ion battery
cells. The X3101 is designed to operate with three (3) Li-ion
battery cells. The CELLN bit of the configuration register
(Table 9) sets the number of cells recognized. For the
X3101, the value for CELLN should always be zero.
Table 9. Selection of Number of Battery Cells1
The configuration register consists of 16 bits of
NOVRAM memory (Table 2, Table 3). This memory
features a high-speed static RAM (SRAM) overlaid bit-
for-bit with non-volatile “Shadow” EEPROM. An auto-
matic array recall operation reloads the contents of the
shadow EEPROM into the SRAM configuration regis-
ter upon power-up (Figure 1).
Figure 1. Power-up of Configuration Register
The configuration register is designed for unlimited
write operations to SRAM, and a minimum of
1,000,000 store operations to the EEPROM. Data
retention is specified to be greater than 100 years.
It should be noted that the bits of the shadow
EEPROM are for the dedicated use of the configura-
tion register, and are NOT part of the general purpose
4kbit EEPROM array.
T
he WCFIG command writes to the configuration reg-
After writing to this register using a WCFIG instruction,
data will be stored only in the SRAM of the configura-
tion register. In order to store data in shadow
EEPROM, a WREN instruction, followed by a
EEWRITE to any address of the 4kbit EEPROM mem-
ory array must occur, see Figure 2. This sequence ini-
tiates an internal nonvolatile write cycle which permits
data to be stored in the shadow EEPROM cells. It
must be noted that even though a EEWRITE is made
to the general purpose 4kbit EEPROM array, the value
and address to which it is written, is unimportant. If this
procedure is not followed, the configuration register
will power-up to the last previously stored values fol-
lowing a power-down sequence.
Configuration
Register Bit
Operation
CELLN
1
4 Li-Ion battery cells (X3100 default)
0
3 Li-Ion battery cells (X3100 or X3101)
1. In the case that the X3100 or X3101 is configured for use with
only three Li-Ion battery cells (i.e. CELLN = 0), then VCELL4
(pin 7) MUST be tied to Vss (pin 9) to ensure correct operation.
Configuration Register (SRAM)
Shadow EEPROM
Recall
Upper Byte
Lower Byte
X3100, X3101
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