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參數(shù)資料
| 型號(hào)： | X1209 |
| 英文描述： | Real Time Clock/Calendar with Event/Timestamp Detection & Alarms(帶有事件/時(shí)間標(biāo)記檢測(cè)與報(bào)警功能的實(shí)時(shí)時(shí)鐘/日歷) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷的事件/時(shí)間戳檢測(cè) |
| 文件頁(yè)數(shù)： | 18/27頁(yè) |
| 文件大?。?/td> | 511K |
| 代理商： | X1209 |
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Preliminary Information
X1209
18 of 27
REV 3.0 2/11/04
www.xicor.com
Table 5. Digital Trimming Registers
ALARM REGISTER
Addresses [0C hex to 11hex]
The alarm register contents mimic the contents of the
RTC register, but add enable bits and exclude the 24
hour time selection bit. The enable bits specify which
registers to use in the comparison between the Alarm
and Real Time Registers. For example:
– Setting the Enable Month Bit (EMNA) bit in combina-
tion with other enable bits and a specific alarm time,
the user can establish an alarm that triggers at the
same time once a year.
When there is a match, an alarm flag (ALM) is set. The
occurrence of an alarm can be determined by polling
the ALM bit or by enabling the IRQ output, using it as
hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1209 to alarm every Wednes-
day at 8:00 AM by setting the EDWA, the EHRA and
EMNA enable bits to ‘1’ and setting the DWA, HRA
and MNA Alarm registers to 8:00AM Wednesday.
– A daily alarm for 9:30PM results when the EHRA and
EMNA enable bits are set to ‘1’ and the
HRA and MNA registers are set to 9:30PM.
USER REGISTER (USER)
Addresses [12 hex to 13 hex]
These registers are available for (2 bytes) user memory
storage.
DTR Register
DTR2
DTR1
0
0
0
0
1
1
1
1
Estimated frequency
PPM
0 (default)
+20
+40
+60
0
-20
-40
-60
DTR0
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
1
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