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參數(shù)資料
| 型號： | X1209 |
| 英文描述： | Real Time Clock/Calendar with Event/Timestamp Detection & Alarms(帶有事件/時間標(biāo)記檢測與報警功能的實時時鐘/日歷) |
| 中文描述： | 實時時鐘/日歷的事件/時間戳檢測 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 511K |
| 代理商： | X1209 |
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Preliminary Information
X1209
14 of 27
REV 3.0 2/11/04
www.xicor.com
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time
being read. A sequential read of the CCR will not result
in the output of data from the memory array. At the end
of a read, the master supplies a stop condition to end
the operation and free the bus. After a read of the
CCR, the address remains at the previous address +1
so the user can execute a current address read of the
CCR and continue reading the next Register.
REAL TIME CLOCK REGISTERS
Addresses [00 hex to 06hex]
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) can be either a 12-hour or 24-
hour mode, (MIL bit = 0) the HR provides 1 to 12 with
an AM or PM indicator (H21 bit) or 0 to 23 (with MIL bit
= 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR
(Year) is 0 to 99.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DW2 to DW0 to represent the seven
days of the week. The counter advances in the cycle 0-
1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indica-
tor with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1209 does not correct for
the leap year in the year 2100.
CONTROL AND STATUS REGISTERS
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Event Detec-
tion, Analog Trimming and Digital Trimming Registers.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 07h. This is a volatile register only and
provides either control or status of RTC failure, battery
mode, alarm trigger, event detection, write protection
of clock counter, crystal oscillator enable and auto
reset of status bits.
Table 2. Status Register (SR)
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware (X1209 internally)
when the device powers up after having lost all power
to the device. The bit is set regardless of whether V
CC
or VBAT is applied first. The loss of only one of the sup-
plies does not result in setting the RTCF bit. The first
valid write to the RTC after a complete power failure
(writing one byte is sufficient) resets the RTCF bit to ‘0’.
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from supply from the V
BAT
pin and not the V
CC
pin.
This bit can be reset either manually by the user (note
this bit can only be manually cleared to 0) or automati-
cally reset by enabling the auto-reset bit (see ARST
bit).
AL: Alarm bit—Volatile
These bits announce if the alarm matches the real time
clock. If there is a match, the respective bit is set to ‘1’.
This bit can be reset either manually by the user (note
this bit can only be manually cleared to 0) or automati-
cally reset by enabling the auto-reset bit (see ARST
bit).
Addr
07h
7
6
5
4
3
2
1
0
A
X
r
W
E
A
B
R
Default
0
0
0
0
0
0
0
1
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