參數(shù)資料
型號(hào)： X1209
英文描述： Real Time Clock/Calendar with Event/Timestamp Detection & Alarms(帶有事件/時(shí)間標(biāo)記檢測(cè)與報(bào)警功能的實(shí)時(shí)時(shí)鐘/日歷)
中文描述： 實(shí)時(shí)時(shí)鐘/日歷的事件/時(shí)間戳檢測(cè)
文件頁(yè)數(shù)： 15/27頁(yè)
文件大小： 511K
代理商： X1209
15 of 27
REV 3.0 2/11/04
www.xicor.com
Preliminary Information
X1209
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
EVT: Event Detection bit —Volatile
The event detection bit provides status of the event
input pin (EVIN). When the EVIN pin is triggered the
EVT bit is set to 1 to indicate a detection of an event
input. This bit can be reset either manually by the user
(note this bit can only be manually cleared to 0) or
automatically reset by enabling the auto-reset bit (see
ARST bit).
When an high signal is present at the EVIN pin, an
“event” is detected. On detection a corresponding bit in
the status register (EVT bit) is set high and the EVDET
pin, open drain, is activated (pulled low).
WRTC: Write RTC Enable Bit—Volatile
The WRTC bit enables or disables write capability into
the RTC Timing Registers. The factory default setting
of this bit is “0”. Upon initialization or power up, the
WRTC must be set to “1” to enable the RTC. Upon the
completion of a valid write (STOP), the RTC starts
counting. The RTC internal 1 Hz signal is synchronized
to the STOP condition during a valid write cycle.
XTOSCB: Crystal Oscillator Enable Bit —Volatile
This bit enables / disables the internal crystal oscillator.
When the XTOSCB is set to “1”, the oscillator is dis-
abled. When the XTOSCB is cleared to “0”, the X1 pin
allows for an external 32kHz signal to drive the RTC.
ARST: Auto Reset Enable Bit —Volatile
This bit enables / disables the automatic reset of the
following status bits only: BAT, ALM, EVT. When ARST
bit is set to “1”, the participating status bits are reset to
“0” after a valid read of the status register (STOP con-
dition). When the ARST is cleared to “0” the user must
manually reset the ARST bit.
INTERRUPT CONTROL REGISTER (INT)
Table 3. Interrupt Control Register (INT)
FO<3:0>: Frequency Out Control Bits - Volatile
These bits enable / disable the frequency output func-
tion and selects the output frequency at the IRQ /
FOUT pin. See Table 3 for frequency selection. When
the frequency mode is enabled it will override the alarm
mode at the IRQ / FOUT pin.
Table 4. Frequency Selection of FOUT pin
Frequency,
FOUT
Default
0
0
Hz
32
kHz
4096
Hz
1024
Hz
64
Hz
32
Hz
16
Hz
8
Hz
4
Hz
2
Hz
1
Hz
1/2
Hz
1/4
Hz
1/8
Hz
1/16
Hz
1/32
Hz
FOBATB: Frequency Output and Interrrupt bit -
Volatile
This bit enables / disables the FOUT / IRQ pin during
battery backup mode (i.e. V
BAT
power source active).
When the FOBATB is set to “1” the FOUT / IRQ pin is
disabled during battery backup mode. When the
FOBATB is cleared to “0” the FOUT / IRQ pin is
enabled during battery backup mode.
Addr
08h
7
6
5
4
3
2
1
0
I
A
L
F
F
F
F
F
Default
0
0
0
0
0
0
0
1
Units
FO3
FO2
FO1
FO0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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