參數(shù)資料
型號(hào)： X1202
英文描述： Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/CPU監(jiān)控電路)
中文描述： 實(shí)時(shí)時(shí)鐘/日歷/報(bào)警/ CPU監(jiān)控（實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/ CPU的監(jiān)控電路）
文件頁(yè)數(shù)： 9/23頁(yè)
文件大小： 340K
代理商： X1202
X1202
Characteristics subject to change without notice.
9 of 23
REV 1.1.8 5/17/01
www.xicor.com
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 8.
Figure 8. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 9.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 10.
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
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