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參數(shù)資料
| 型號： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實時時鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實時時鐘/日歷/報警/ CPU監(jiān)控（實時時鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁數(shù)： | 10/23頁 |
| 文件大小： | 340K |
| 代理商： | X1202 |
X1202
Characteristics subject to change without notice.
10 of 23
REV 1.1.8 5/17/01
www.xicor.com
Figure 10. Acknowledge Response From Receiver
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct device
identifier and select bits are contained in the slave
address byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The slave address byte when the device identifier
and/or select bits are incorrect
– All data bytes of a write when the WEL in the write
protect register is LOW
– The 2nd data byte of a status register write operation
(only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to standby mode and place the
device into a known state.
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
slave address byte and the CCR address bytes. This
gives the master access to any one of the words in the
CCR. (
Note:
Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceeding operations to enable the write operation.
See “Writing to the Clock/Control Registers” on page 6.)
Upon receipt of each address byte, the X1202
responds with an acknowledge. After receiving both
address bytes the X1202 awaits the eight bits of data.
After receiving the 8 data bits, the X1202 again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition. The
X1202 then begins an internal write cycle of the data to
the nonvolatile memory. During the internal write cycle,
the device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 11.
Page Write
The X1202 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 7
more bytes to the clock/control registers.
Note:
Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceeding operations to enable the write operation. See
“Writing to the Clock/Control Registers” on page 6.)
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