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參數(shù)資料
| 型號： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實時時鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實時時鐘/日歷/報警/ CPU監(jiān)控（實時時鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 340K |
| 代理商： | X1202 |
X1202
Characteristics subject to change without notice.
18 of 23
REV 1.1.8 5/17/01
www.xicor.com
Write Cycle Timing
Power Up Timing
Notes:
(1) Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for T
A
= 25°C and V
CC
= 5.0V
Nonvolatile Write Cycle Timing
Note:
(1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Symbol
t
PUR
(1)
t
PUW
(1)
Parameter
Min.
Typ.
(2)
Max.
1
5
Unit
ms
ms
Time from power up to read
Time from power up to write
Symbol
t
WC
(1)
Parameter
Min.
Typ.
(1)
5
Max.
10
Unit
ms
Write cycle time
Symbol
V
PTRIP
Parameter
Min.
Typ.
Max.
Unit
Pre-programmed reset trip voltage
X1202-4.5A
X1202
X1202-2.7A
X1202-2.7
V
CC
detect to RESET LOW
Power up reset time out delay
V
CC
fall time
V
CC
rise time
Watchdog timer period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
4.49
4.25
2.76
2.57
4.63
4.38
2.85
2.65
4.77
4.51
2.94
2.73
500
400
V
t
RPD
t
PURST1
t
F
t
R
t
WDO
ns
ms
μs
μs
100
10
10
200
1.7
725
225
225
1
1.0
1.75
750
250
250
1.8
775
275
275
s
ms
ms
ms
μs
V
t
RST1
t
RSP
V
RVALID
Watchdog reset time out delay
2-wire interface
Reset valid V
CC
SCL
SDA
t
WC
8
th
Bit of Last Byte
ACK
Stop
Condition
Start
Condition
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