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參數(shù)資料
| 型號(hào)： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷/報(bào)警/ CPU監(jiān)控（實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大小： | 340K |
| 代理商： | X1202 |
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X1202
Characteristics subject to change without notice.
8 of 23
REV 1.1.8 5/17/01
www.xicor.com
Figure 5. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
value)
SCL
SDA
01h
RESET
V
P
= 15V
00h
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
AEh
00h
V
CC
V
CC
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is less
than 1.7V. This procedure must be used to set the volt-
age to a lower value.
To reset the new V
TRIP
voltage, apply more than 3V to
the V
CC
pin and tie the RESET pin to the programming
voltage V
P
. Then write 00h to address 03h. The stop bit of
a valid write operation initiates the V
TRIP
programming
sequence. Bring RESET to complete the operation.
Note:
This operation also writes 00h to address 03h of
the EEPROM array.
Figure 6. Reset V
TRIP
Level Sequence (V
CC
> 3V)
Figure 7. Sample V
TRIP
Reset Circuit
0 1 2 3 4 5 6 7
SCL
SDA
AEh
0 1 2 3 4 5 6 7
03h
RESET
V
P
= 15V
00h
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
00h
V
CC
V
CC
1
2
3
4
8
7
6
5
X1202
(8-Pin SOIC)
V
TRIP
Adj
.
V
P
RESET
4.7K
SDA
SCL
μC
Adjust
Run
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