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參數(shù)資料
| 型號： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實時時鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實時時鐘/日歷/報警/ CPU監(jiān)控（實時時鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 340K |
| 代理商： | X1202 |
X1202
Characteristics subject to change without notice.
17 of 23
REV 1.1.8 5/17/01
www.xicor.com
AC SPECIFICATIONS
(T
A
= -40
°
C to +85°C, V
CC
= +2.7V to +5.5V, unless otherwise specified.)
Notes:
(1) Typical values are for T
A
= 25°C and V
CC
= 5.0V
(2) This parameter is periodically sampled and not 100% tested.
(3) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
Cb
Parameter
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
Max.
400
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
pF
SCL clock frequency
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus must be free before a new transmission can start
Clock LOW time
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
SDA and SCL rise time
SDA and SCL fall time
Capacitive load for each bus line
0.9
20 +.1Cb
(3)
20 +.1Cb
(3)
300
300
400
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
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