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參數(shù)資料
| 型號(hào)： | X1202 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/CPU監(jiān)控電路) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷/報(bào)警/ CPU監(jiān)控（實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/ CPU的監(jiān)控電路） |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 340K |
| 代理商： | X1202 |
X1202
Characteristics subject to change without notice.
5 of 23
REV 1.1.8 5/17/01
www.xicor.com
Clock/Calendar Register (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 0 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date)
is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and bit H21 functions as an AM/PM indica-
tor with a ‘1’ representing PM. The clock defaults to
Standard Time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1202 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003Fh. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read two power status and two alarm bits. This
register is separate from both the array and the Clock/
Control Registers (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V
BACK
, not V
CC
. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm bits—Volatile
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags.
Note:
starts will be reset. An alarm bit that is set by an alarm
occurring during an SR read operation will remain set
after the read operation is complete.
Only the AL bits that are set when an SR read
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence. RWEL bit is reset after each high voltage or
reset by sending 00h to status register.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to “0” (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part pow-
ers up again. Writes to WEL bit do not cause a nonvol-
atile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
bit is set regardless of whether V
applied first. The loss of one or the other supplies does
not result in setting the RTCF bit. The first valid write to
the RTC (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
CC
or V
BACK
is
Unused Bits
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output during
a SR read will contain zeros in these bit locations.
CONTROL REGISTER
Watchdog Timer Control Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 3 for options.
Addr
7
6
5
4
3
2
1
0
003Fh
BAT
AL1
AL0
0
0
RWEL
WEL
RTCF
Default
0
0
0
0
0
0
0
1
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