參數(shù)資料
型號(hào): WM8773
廠商: Wolfson Microelectronics
元件分類: ADC
英文描述: 24-bit, 96kHz ADC with 8 Channel I/P Multiplexer
中文描述: 24位,96kHz的ADC,具有8通道I /頁復(fù)用器
文件頁數(shù): 19/30頁
文件大?。?/td> 270K
代理商: WM8773
Product Preview
WM8773
PP Rev 1.0 June 2002
19
Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC
and BCLK are outputs and are generated by the WM8773. In Slave mode ADCLRC and BCLK are
inputs to WM8773.
REGISTER ADDRESS
10111
Interface Control
BIT
8
LABEL
MS
DEFAULT
0
DESCRIPTION
Audio Interface Master/Slave Mode
select:
0 : Slave Mode
1: Master Mode
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8773 generates ADCLRC and BCLK. These clocks are derived from master
clock and the ratio of MCLK to ADCLRC and are set by ADCRATE.
REGISTER ADDRESS
0111 ADCLRC frequency
select
BIT
2:0
LABEL
DEFAULT
010
DESCRIPTION
ADCRATE[2:0]
Master Mode MCLK:ADCLRC
ratio select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the
ADC signal processing oversample rate to 64fs.
REGISTER ADDRESS
10111
ADC Oversampling Rate
BIT
3
LABEL
ADCOSR
DEFAULT
0
DESCRIPTION
ADC oversampling rate select
0: 128x oversampling
1: 64x oversampling
MUTE MODES
Each ADC channel has an individual mute control bit, which mutes the input to the ADC. In addition
both channels may be muted by setting ADCMUTE.
REGISTER ADDRESS
11001
ADC Mute
BIT
7
LABEL
ADCMUTE
DEFAULT
0
DESCRIPTION
ADC MUTE Left and Right
0 : Normal Operation
1: mute ADC left and ADC
right
ADC Mute select
0 : Normal Operation
1: mute ADC left
ADC Mute select
0 : Normal Operation
1: mute ADC right
11001
ADC Mute Left
5
MUTE
0
11010
ADC Mute Right
5
MUTE
0
The Record outputs may be enabled by setting RECEN, where RECEN enables the RECL and
RECR outputs.
REGISTER ADDRESS
10100
REC Enable
BIT
5
LABEL
RECEN
DEFAULT
0
DESCRIPTION
REC Output Enable
0 : REC output muted
1: REC output enabled
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