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參數(shù)資料
| 型號： | WM8773 |
| 廠商： | Wolfson Microelectronics |
| 元件分類： | ADC |
| 英文描述： | 24-bit, 96kHz ADC with 8 Channel I/P Multiplexer |
| 中文描述： | 24位，96kHz的ADC，具有8通道I /頁復用器 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 270K |
| 代理商： | WM8773 |
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WM8773
Product Preview
PP Rev 1.0 June 2002
18
CONTROL INTERFACE REGISTERS
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
REGISTER ADDRESS
10110
Interface Control
BIT
1:0
LABEL
FMT[1:0]
DEFAULT
10
DESCRIPTION
Interface format Select
00 : right justified mode
01: left justified mode
10: I
2
S mode
11: DSP (early or late) mode
In left justified, right justified or I
2
S modes, the LRP register bit controls the polarity of ADCLRC. If
this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 9, and.
Note that if this feature is used as a means of swapping the left and right channels, a 1 sample
phase difference will be introduced. In DSP modes, the LRP register bit is used to select between
early and late modes.
REGISTER ADDRESS
10110
Interface Control
BIT
2
LABEL
LRP
DEFAULT
0
DESCRIPTION
In left/right/I
2
S modes:
ADCLRC Polarity (normal)
0 : normal ADCLRC polarity
1: inverted ADCLRC polarity
In DSP mode:
0 : Early DSP mode
1: Late DSP mode
By default, ADCLRC is sampled on the rising edge of BCLK and should ideally change on the falling
edge. Data sources that change ADCLRC on the rising edge of BCLK can be supported by setting
the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in
Figure 9, Figure 10, Figure 11, Figure 12, and Figure 13.
REGISTER ADDRESS
10110
Interface Control
BIT
3
LABEL
BCP
DEFAULT
0
DESCRIPTION
BCLK Polarity (DSP modes)
0 : normal BCLK polarity
1: inverted BCLK polarity
The WL[1:0] bits are used to control the word length.
REGISTER ADDRESS
10110
Interface Control
BIT
5:4
LABEL
WL[1:0]
DEFAULT
10
DESCRIPTION
Word Length
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
Note:
1.
If 32-bit mode is selected in right justified mode, the WM8773 defaults to 24 bits.
2.
In 24 bit I
2
S mode, any width of 24 bits or less is supported provided that ADCLRC is high for a
minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
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相關代理商/技術參數(shù) |
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| WM8774 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:24 - bit, 192kHz 8 - Channel Input Stereo Codec |
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