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參數(shù)資料
| 型號： | WED3DL328V10BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119 |
| 封裝： | 14 X 22 MM, MO-163, BGA-119 |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 1195K |
| 代理商： | WED3DL328V10BC |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after
the clock.
3. Access time from Row active command. tCC *(tRCD + CAS# latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
RAS#
CAS#
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE#
Rb
Cb0
Ca0
Ra
CL = 2
DQ
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
WE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
tRCD
tRC
Rb
Note 1
Ra
Qa0
tSHZ
tRDL
tRAC
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
tSAC
tOH
Note 3
Note 4
Note 3
DON'T CARE
Note 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED3DL328V10BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V8BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX32|CMOS|BGA|119PIN|PLASTIC |
| WED3DL328V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
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