參數(shù)資料
型號(hào): WED3DL328V10BC
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119
封裝: 14 X 22 MM, MO-163, BGA-119
文件頁數(shù): 18/27頁
文件大?。?/td> 1195K
代理商: WED3DL328V10BC
25
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE
NOTES:
TO ENTER SELF REFRESH MODE
1. CE#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low.”
Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CE# starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
RAS#
CAS#
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE#
DQ
Auto Refresh
Self Refresh Entry
Self Refresh Exit
WE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tSS
DON'T CARE
Note 1
Note 3
Note 4
tRFC min
Note 6
Note 5
Note 7
HI-Z
Note 2
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