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參數(shù)資料
| 型號(hào)： | WED3DL328V10BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119 |
| 封裝： | 14 X 22 MM, MO-163, BGA-119 |
| 文件頁(yè)數(shù)： | 3/27頁(yè) |
| 文件大?。?/td> | 1195K |
| 代理商： | WED3DL328V10BC |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current Sate then
the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satised.
7. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satied.
Current State
Command
Action
Notes
CE#
RAS#
CAS#
WE#
BA0-1
A11,
A10/AP-A0
Description
Refreshing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
No Operation; Idle after tRC
L
H
X
No Operation
No Operation; Idle after tRC
H
X
Device Deselect
No Operation; Idle after tRC
Mode Register
Accessing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
ILLEGAL
L
H
X
No Operation
No Operation; Idle after two clock cycles
H
X
Device Deselect
No Operation; Idle after two clock cycles
CURRENT STATE TRUTH TABLE (CONT.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED3DL328V10BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V8BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX32|CMOS|BGA|119PIN|PLASTIC |
| WED3DL328V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
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