參數(shù)資料
型號: WED3DL328V10BC
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119
封裝: 14 X 22 MM, MO-163, BGA-119
文件頁數(shù): 4/27頁
文件大?。?/td> 1195K
代理商: WED3DL328V10BC
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1
3. Enable and disable auto precharge function are controlled by A10/AP in read/write
command.
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.
BA0
BA1
Active & Read/Write
0
Bank A
0
1
Bank B
1
0
Bank C
1
Bank D
NOTES:
1. All input except CKE & DQM can be don’t care when CE# is high at the CLK high
going edge.
2. Bank active & read/write are controlled by BA0~BA1.
A10/AP BA0 BA1
Precharge
0
Bank A
0
1
Bank B
0
1
0
Bank C
0
1
Bank D
1
x
All Banks
A10/AP BA0 BA1
Operation
0
Distribute auto precharge, leave bank A active at end of burst.
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
1
Disable auto precharge, leave bank D active at end of burst.
1
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
Enable auto precharge, precharge bank D at end of burst.
RAS#
CAS#
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE#
Cb
Cc
Rb
Ca
Ra
DQ
Row Active
Precharge
Read
Write
Read
Row Active
Db
Qc
WE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
tRCD
tRP
tRAS
tRCD
BS
Note 3
Note 4
Rb
Note 3
Note 2, 3
Note 2
Note 4
Note 2, 3
Ra
BS
Qa
tOH
tSAC
tSLZ
tRAC
tSS
tSH
tCCD
tCH
tCL
tCC
DON'T CARE
Note 2
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
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