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參數(shù)資料
| 型號： | W986432DH-7L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| 封裝： | 0.400 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 1648K |
| 代理商： | W986432DH-7L |
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W986432DH
Publication Release Date: July 30, 2002
- 17 -
Revision A5
5. Power up Sequence
(1) Power up must be performed in the following sequence.
(2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the "NOP" state. The CLK
signals must be started at the same time.
(3) After power-up a pause of at least 200
S is required. It is required that DQM and CKE signals then be held "high"
(VCC levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.
6. AC Testing Conditions
PARAMETER
CONDITIONS
Output Reference Level
1.4V
Output Load
See diagram below
Input Signal Levels (VIH/VIL)
2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal
1 nS
Input Reference Level
1.4V
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohms
output
30pF
1.
Transition times are measured between VIH and VIL.
2.
tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
3.
These parameters account for the number of clock cycles and depend on the operating frequency of the clock,
as follows the number of clock cycles = specified value of timing/ clock period
(count fractions as whole number)
(1) tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).
tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).
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