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參數(shù)資料
| 型號： | W947D6HBHX6E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 1160K |
| 代理商： | W947D6HBHX6E |
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W947D6HB / W947D2HB
128Mb Mobile LPDDR
Publication Release Date:Jun,17, 2011
- 24 -
Revision A01-003
Notes:
1.
The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was
Self Refresh or Power Down.
2.
DESELECT and NOP are functionally interchangeable.
3.
All states and sequences not shown are illegal or reserved.
4.
Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
5.
Read with AP enabled and Write with AP enabled: The read with Auto Precharge enabled or Write with Auto Precharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge
period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest
possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the precharge
period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with
registration of the command and ends where the precharge period (or tRP) begins. During the precharge period, of the
Read with Auto Precharge enabled or Write with Auto Precharge enabled states, ACTIVE, PRECHARGE, READ, and
WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands
to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data
and WRITE data must be avoided).
6.
AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
7.
A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
8.
READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs
and WRITEs with Auto Precharge disabled.
9.
Requires appropriate DM masking.
10.
A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must
be issued to end the READ prior to asserting a WRITE command.
7. OPERATION
7.1. Deselect
The DESELECT function ( CS = high) prevents new commands from being executed by the LPDDR SDRAM. The
LPDDR SDRAM is effectively deselected. Operations already in progress are not affected.
7.2. No Operation
The NO OPERATION (NOP) command is used to perform a NOP to a LPDDR SDRAM that is selected ( CS =Low).
This prevents unwanted commands from being registered during idle or wait states. Operations already in progress
are not affected.
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| W9712G8JB-3 | DDR DRAM, PBGA60 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W947D6HBHX6G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W948D2FB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:256Mb Mobile LPDDR |
| W948D2FBJX5E | 功能描述:IC LPDDR SDRAM 256MBIT 90VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W948D2FBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ |
| W948D2FBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
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