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參數(shù)資料
| 型號(hào)： | W9425G8DH-6 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 |
| 文件頁數(shù)： | 53/53頁 |
| 文件大小： | 1920K |
| 代理商： | W9425G8DH-6 |
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W9425G8DH
Publication Release Date: Nov. 20, 2007
- 9 -
Revision A4
7. FUNCTIONAL DESCRIPTION
7.1 Power Up Sequence
(1) Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined
1) Apply VDD before or at the same time as VDDQ.
2) Apply VDDQ before or at the same time as VTT and VREF.
(2) Start Clock and maintain stable condition for 200 S (min.).
(3) After stable power and clock, apply NOP and take CKE high.
(4) Issue precharge command for all banks of the device.
(5) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
(6) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(An additional 200 cycles(min) of clock are required for DLL Lock before any executable
command applied.)
(7) Issue precharge command for all banks of the device.
(8) Issue two or more Auto Refresh commands.
(9) Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.
7.2 Command Function
7.2.1
Bank Activate Command
( RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address)
The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row
addresses are latched on A0 to A12 when this command is issued and the cell data is read out of
the sense amplifiers. The maximum time that each bank can be held in the active state is specified
as tRAS (max). After this command is issued, Read or Write operation can be executed.
7.2.2
Bank Precharge Command
( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don’t
Care)
The Bank Precharge command percharges the bank designated by BS. The precharged bank is
switched from the active state to the idle state.
7.2.3
Precharge All Command
( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don’t Care, A10 = "H", A0 to A9, A11, A12 =
Don’t Care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to
the idle state.
7.2.4
Write Command
( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9 = Column Address)
The write command performs a Write operation to the bank designated by BS. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9425G8EH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M × 4 BANKS × 8 BITS DDR SDRAM |
| W946432AD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K X 4 BANKS X 32 BITS DDR SDRAM |
| W9464G6IB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM |
| W9464G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ?? 4 BANKS ?? 16 BITS DDR SDRAM |
| W9464G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ? 4 BANKS ? 16 BITS DDR SDRAM |
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