參數(shù)資料
型號: W9425G8DH-6
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 32M X 8 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 21/53頁
文件大?。?/td> 1920K
代理商: W9425G8DH-6
W9425G8DH
Publication Release Date: Nov. 20, 2007
- 28 -
Revision A4
Continued
-5
-6
SYM.
PARAMETER
MIN.
MAX.
MIN.
MAX.
UNIT
NOTES
tIS
Input Setup Time
0.6
0.75
tIH
Input Hold Time
0.6
0.75
tIPW
Control & Address Input Pulse Width (for each input)
2.2
tHZ
Data-out High-impedance Time from CLK, CLK
-0.7
0.7
-0.7
0.7
tLZ
Data-out Low-impedance Time from CLK, CLK
-0.7
0.7
-0.7
0.7
tT(SS)
SSTL Input Transition
0.5
1.5
0.5
1.5
nS
tWTR
Internal Write to Read Command Delay
2
1
tCK
tXSNR
Exit Self Refresh to non-Read Command
75
72
nS
tXSRD
Exit Self Refresh to Read Command
200
tCK
tREFI
Refresh Time (8k)
7.8
S
tMRD
Mode Register Set Cycle Time
10
12
nS
9.7 AC Test Conditions
PARAMETER
SYMBOL
VALUE
UNIT
Input High Voltage (AC)
VIH
VREF + 0.31
V
Input Low Voltage (AC)
VIL
VREF - 0.31
V
Input Reference Voltage
VREF
0.5 x VDDQ
V
Termination Voltage
VTT
0.5 x VDDQ
V
Differential Clock Input Reference Voltage
VR
Vx (AC)
V
Input Difference Voltage. CLK and CLK Inputs (AC)
VID (AC)
1.5
V
Output Timing Measurement Reference Voltage
VOTR
0.5 x VDDQ
V
V SWING (MAX)
VDDQ
VSS
T
VIH min (AC)
VREF
VIL max (AC)
SLEW = (VIHmin (AC) - VILmax (AC)) / T
Output
50 Ω
VTT
Timing Reference Load
Output
V(out)
30pF
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