參數(shù)資料
型號(hào)： W9425G8DH-6
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： DRAM
英文描述： 32M X 8 DDR DRAM, 0.7 ns, PDSO66
封裝： 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁(yè)數(shù)： 51/53頁(yè)
文件大?。?/td> 1920K
代理商： W9425G8DH-6
W9425G8DH
Publication Release Date: Nov. 20, 2007
- 7 -
Revision A4
5. PIN DESCRIPTION
PIN NUMBER PIN NAME
FUNCTION
DESCRIPTION
28
32,
35
42
A0
A12
Address
Multiplexed pins for row and column address.
Row address: A0
A12.
Column address: A0
A9. (A10 is used for Auto-precharge)
26, 27
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or bank
to read/write during column address latch time.
2, 5, 8, 11, 56,
59, 62, 65
DQ0
DQ7
Data Input/
Output
The DQ0 – DQ7 input and output data are synchronized with
both edges of DQS.
51
DQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
24
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
RAS , CAS ,
WE
Command
Inputs
Command inputs (along with CS ) define the command being
entered.
47
DM
Write Mask
When DM is asserted
"high" in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45, 46
CLK, CLK
Differential
Clock Inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK
.
44
CKE
Clock Enable
CKE controls the clock activation and deactivation. When CKE
is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
49
VREF
Reference
Voltage
VREF is reference voltage for inputs.
1, 18, 33
VDD
Power (+2.5) Power for logic circuit inside DDR SDRAM.
34, 48, 66
VSS
Ground
Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
VDDQ
Power (+2.5V)
for I/O Buffer
Separated power from VDD, used for output buffer, to improve
noise.
6, 12, 52, 58, 64
VSSQ
Ground for I/O
Buffer
Separated ground from VSS, used for output buffer, to improve
noise.
4, 7, 10, 13, 14,
16, 17, 19, 20,
25, 43, 50, 53,
54, 57, 60, 63
NC
No Connection
No connection. (NC pin should be connected to GND or
floating)
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