參數(shù)資料
型號(hào): W9412G6IH-6I
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, ROHS COMPLIANT, TSOP2-66
文件頁(yè)數(shù): 8/53頁(yè)
文件大小: 825K
代理商: W9412G6IH-6I
W9412G6IH
Publication Release Date: Sep. 16, 2009
- 16 -
Revision A06
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
A5
A4
CAS LATENCY
0
Reserved
0
1
Reserved
0
1
0
2
0
1
3
1
0
4
1
0
1
Reserved
1
0
2.5
1
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
7.10.5 Mode Register/Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1
BA0
A11-A0
0
Regular MRS Cycle
0
1
Extended MRS Cycle
1
x
Reserved
7.10.6 Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0
DLL
0
Enable
1
Disable
2) Output Driver Strength Control field (A6, A1)
The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode
Register Set (EMRS) as the following:
A6
A1
BUFFER STRENGTH
0
100% Strength
0
1
60% Strength
1
0
Reserved
1
30% Strength
7.10.7 Reserved field
Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to “0” for normal operation.
Reserved bits (A9, A10, A11)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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