參數(shù)資料
型號: W9412G6IH-6I
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 7/53頁
文件大小: 825K
代理商: W9412G6IH-6I
W9412G6IH
Publication Release Date: Sep. 16, 2009
- 15 -
Revision A06
7.10.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both
addressing Mode support burst length 2, 4 and 8 words.
A3
ADDRESSING MODE
0
Sequential
1
Interleave
7.10.2.1. Addressing Sequence of Sequential Mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
Addressing Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
2 words (address bits is A0)
Data 1
n + 1
not carried from A0 to A1
Data 2
n + 2
4 words (address bit A0, A1)
Data 3
n + 3
Not carried from A1 to A2
Data 4
n + 4
Data 5
n + 5
8 words (address bits A2, A1 and A0)
Data 6
n + 6
Not carried from A2 to A3
Data 7
n + 7
7.10.2.2. Addressing Sequence for Interleave Mode
A Column access is started from the inputted column address and is performed by interleaving the
address bits in the sequence shown as the following.
Addressing Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
8 words
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
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