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參數(shù)資料
| 型號(hào)： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 59/72頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | W89C840F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 59 -
R03, Receive Descriptor 3
The R03 is used to specify the start address of the receive buffer 2
Bit
Symbol
Description
31:0
RBA2
Receive Buffer Address 2
The RBA2 indicates the physical address, in the system memory space, of the
second transmit buffer pointed by the current descriptor. The RBA2 must be
longword aligned. It is valid on each descriptor of the current frame.
Transmit Descriptors
T00, Transmit Descriptor 0
The T00 is used to describe the transmited frame status.
After the current frame is transmitted, the transmit DMA state machine will update the valid status
of the current transmitted frame into the last descriptor of the current transmitted frame.
The Transmit Access Control is valid on each descriptor of the current frame. The transmit DMA
state machine will release the descriptor by reset the TAC bit when the data pointed by this descriptor is
transmitted.
Bit
Symbol
Description
31
TAC
Transmit Access Control :
When the TAC bit is set, the current descriptor allows to be accessed by
W89C840F, otherwise the W89C840F can not issue any read or write request on
this descriptor. When the TAC is reset to low, the driver program is allowed to
access this descriptor.
This bit will be reset before completing to fill data into the transmit buffer; set if
the data in the transmit buffer is available.
It is a valid value on each descriptor of the current frame.
15
TE
Transmit Error:
It indicates any one of the following events occurs when TE is set to high.
T00[1] -- Transmit FIFO underflow
T00[8] -- Transmit aborted
T00[10] -- No Carrier sense
T00[11] -- Carrier sense lost
This bit is valid only when the bit TLD (T01[30]) is set, i.e when the current
descriptor is the last descriptor of the current frame.
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