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參數(shù)資料
| 型號(hào)： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 22/72頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | W89C840F |
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W89C840F
- 22 -
EEPROM hardware reset auto load and software programming function
The following configuration parameters should be stored in a EEPROM device for configuring
the W89C840F and can be loaded into the corresponding configuration register while power-on reset
occurring.
1) the 6 bytes Ethernet ID.
2) the 2 bytes subsystem ID.
3) the 2 bytes subsystem vendor ID.
4) the 2 bytes device ID.
5) the 2 bytes vendor ID.
6) the 1 bytes revision ID.
7) the 1 byte booting device size
8) the 1 byte maximum latency
9) the 1 byte minimum grant
The data mapping and its offset address for all of the above parameters are as the following
table.
Address
High Byte (BIT 15 ~ BIT 8)
Low Byte (BIT 7 ~ BIT 0)
09H~3FH
reserved
reserved
08H
C48
Revision ID
07H
Vendor ID(high byte)
Vendor ID(low byte)
06H
Device ID(high byte)
Device ID(low byte)
05H
Subsystem Vendor ID(high byte)
Subsystem Vendor ID(low byte)
04H
Subsystem ID(high byte)
Subsystem ID(Low byte)
03H
MAXLAT
MINGNT
02H
Ethernet Address 5
Ethernet Address 4
01H
Ethernet Address 3
Ethernet Address 2
00H
Ethernet Address 1
Ethernet Address 0
The W89C840F will generate a nine-word reading command to the EEPROM to read the
configuration data and store these data into the configuration registers and the control register of the
W89C840F after hardware reset. The serial EEPROM 93C06 or 93C46 will be the choice as the
storage device for storing these configuration data.
Oher than bei ng read
after hardware reset, the EEPROM can be read by the application
program. The C24/CMIIR register provides an alternative path to access the data in EEPROM. The
bits 0, 1, 2, ... and 7 of CMIIR are general I/O port. Wh
en the bi t 11 of CMIR i s set
high,
the
bits 0, 1 and 2 will be
respecti vel y
put on the EECS, BtAdata1/EECK, and
BtAdata2/EEDI
to
trigger EEPROM. The data from EEPROM running over the pin BtAdata3/EEDO will be hold and
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