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參數(shù)資料
| 型號(hào)： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 31/72頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | W89C840F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 31 -
F30/FERBA Expansion ROM Base Address Register
This register is written by power-on software
to specify the on-board boot ROM base address in the system.
Bit
Attribute
Bit name
Description
31:13
R/W
EROMB
Expansion ROM Base Address.
Written by power-on software to specify expansion ROM base
address.
The W89C840F w l l request u
p to 256K bytes memory space for
the on board boot ROM device according the configuration of
C48/CBRCR.
The return back read value of bit 0 to bit 17 of F30/FERBA will
depend on the configuration of C48/CBRCR.
12:1
R
---
Reserved. Fixed at 0.
0
R/W
ROME
Expansion ROM Enable.
Set both this bit and F04/FCS bit 1 to 1 to enable expansion ROM
access ability. The F04/FCS bit 1 has precedence over this bit.
F3C/FIR Interrupt Register
The upper half of this register is loaded from external serial EEPROM while the lower half is written
.
The
W89C840F will issue a Retry signal to host when the host tries to access to this register while the EEPROM
auto-loading is not yet completed.
Bit
Attribute
Bit name
Description
31:24
R
MAXLAT
Max_Lat.
This indicates how often, in units of 0.25
μ
S, the W89C840F needs
to gain
access to PCI bus. Assuming PCI clock rate is 33 MHz.
23:16
R
MINGNT
Min_Gnt.
This indicates how long a burst period, in units of 0.25
μ
S, is needed
by the W89C840F. Assuming PCI clock rate is 33 MHz.
15:8
R
IPIN
Interrupt Pin.
Fixed at 01H to indicate INTA# is used.
7:0
R/W
ILINE
Interrupt Line.
Written by power-on software to specify routing of interrupt line.
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