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參數(shù)資料
| 型號(hào)： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 27/72頁(yè) |
| 文件大小： | 731K |
| 代理商： | W89C840F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 27 -
F00/FID Device ID Register
The register F00/FID specifies the vendor ID and the particular device ID in the W89C840F.
Bit
Attribute
Bit name
Description
31:16
R
DID
Device ID. Loaded from EEPROM after hardware reset de-asserted.
15:0
R
VID
VendorID. Loaded from EEPROM after hardware reset de-asserted.
F04/FCS Command and Status Register
The
F04/FCS compri ses two parts,
one is the command register (FCS[15:0]) which provides
the control of 840 PCI activity, and the other is the status register (FCS[31:16]) which shows the status
information of PCI event.
Writing 00h to the command registers will put W89C840F logically isolated from
all PCI access
except configuration access.
Writing 1 to the bits of the status register will clear them; writing 0 has no effect.
Bit
Attribute
Bit name
Description
31
R/W
DPE
Detected Parity Error.
The DPE will be set if a parity error is detected by W89C840F
even the parity error response bit of F04/FCS(bit 6) is disabled.
30
R/W
SSE
Signaled System Error.
The SSE will be set if W89C840F assert SERRB.
29
R/W
RMA
Received Master Abort.
The RMA will be set if
W89C
840
F
master transaction take
s
a
master abort.
28
R/W
RTA
Received Target Abort.
The RTA will be set if the 840 master transaction is terminated by
a target abort.
27
R/W
STA
Signaled Target Abort.
The STA will be set if the W89C840F slave transactions take a
target abort.
26:25
R
DT
DEVSEL# Timing:
Fixed at 01 to indicate a medium DEVSEL# assert timing.
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