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參數(shù)資料
| 型號： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 36/72頁 |
| 文件大?。?/td> | 731K |
| 代理商： | W89C840F |
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W89C840F
- 36 -
13:8
R/W
BL
Burst Length
BL defines the maximum number of the long words that can be
transferred
within
one
The burst length configuration is as following.
PCI
burst
transaction.
[13:8] Burst Length
---------------------------------------------
00H refer to CA
01H 1 long word
02H 2 long word
04H 4 long word
08H 8 long word
10H 16 long word
20H 32 long word
other reserved
7
R/W
BBE
Buffer With Big Endian
When set, the data buffers are treated with big endian ordering.
When reset, the data buffers are treated with little endian
ordering.
6:2
R/W
SKIP
Skip Length Between Descriptors
This field specifies the skip length between two descriptors (from
the start address of the current descriptor to the start address of
the next descriptor). The unit of the skip length is long word.
The default value after hardware or software reset is 04H.
1
R/W
ARB
Arbitration Between Tx And Rx Processes
When set, the TX process and RX process will have the right to
use the internal bus with the same priority. When reset, the RX
process will have higher priority than TX process with regarding
to the internal bus utilization.
0
R/W
SWR
Software Reset.
Set SWR to high will reset most internal registers (except that
C38, C3c, C40, C44, C48, and PCI Configuration Registers).
The software reset will be lasted for 4 PCI clocks and the bit will
self-clean after software reset completed. If any consequent
access to the W89C840F is coming during this reset process, the
W89C840F will delay asserting TRDY# until the reset process is
completed. This bit is default 0 after hardware reset.
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