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參數(shù)資料
| 型號： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 45/72頁 |
| 文件大小： | 731K |
| 代理商： | W89C840F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 45 -
14
R
---
Reserved. Fixed at 0.
13
R/W
BEE
Bus Error Enable.
The Bus Error Interrupt will be enabled if both AIE(bit 15) and
BEE are set to high, otherwise, the Bus Error Interrupt will be
disabled. The hardware interrupt will be asserted if all of the AIE
bit of the C1C/CIMR, the BEE bit of the C1C/CIMR and the BE bit
of the C14/CISR are set to high at the same time.
12
R
---
Reserved. Fixed at 0.
11
R/W
TEE
Timer Expired Enable.
The Timer Expired Interrupt will be enabled if both AIE(bit 15) and
TEE are set to high, otherwise, the Timer Expired Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bit
AIE in C1C/CIMR, the bit TEE in C1C/CIMR and the bit TE
C14/CISR are set to high at the same time.
10
R/W
TEIE
Transmit Early Interrupt Enable.
The Transmit Early Interrupt will be enabled if both AIE(bit 15)
and TEIE are set to high, otherwise, the Transmit Early Interrupt
will be disabled. The hardware interrupt will be asserted if all of the
bit AIE in C1C/CIMR, the bit TEIE in C1C/CIMR and the bit TEI
in C14/CISR are set to high at the same time.
9
R
---
Reserved. Fixed at 0.
8
R/W
RIE
Receive Idle Enable.
The Receive Idle Interrupt will be enabled if both AIE(bit 15) and
RIE are set to high, otherwise, the Receive Idle Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bit
AIE in C1C/CIMR, the bit RIE in C1C/CIMR and the bit RIDLE in
C14/CISR are set to high.
7
R/W
RBUE
Receive Buffer Unavailable Enable.
The Receive Buffer Unavailable Interrupt will be enabled if both
AIE(bit 15) and RBUE are set to high, otherwise, the Receive
Buffer Unavailable Interrupt will be disabled. The hardware
interrupt will be asserted if all of the bit AIE in C1C/CIMR,the bit
RBUE in C1C/CIMR and the bit RBU in C14/CISR are set to high.
6
R/W
RINTE
Receive Interrupt Enable.
The Receive Interrupt will be enabled if both NIE(bit 16) and
RINTE are set to high, otherwise, the Receive Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bit
NIE in C1C/CIMR, the bit RINTE in C1C/CIMR and the bit RINI
in C14/CISR are set to high.
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