參數(shù)資料
型號: W83C553F-G
英文描述: W83C553F-G Highly Integrated System I/O Controller for Power PCTM (South Bridge) QFP 208
中文描述: W83C553F接枝高度集成的系統(tǒng)I / O控制器的電力PCTM(南橋)QFP封裝208
文件頁數(shù): 80/159頁
文件大?。?/td> 3991K
代理商: W83C553F-G
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
77
PCI Arbiter Control Register (default = 80h)
Type:
Read/Write
Bit Description
:
Bit 7:
GAT. Guaranteed Access Timing. If set to a 1b, this bit enables Function 0 Flush Request and
Flush Acknowledge operation on pins 6 and 7 (provided pin 13 is not pulled low after reset).
This bit defaults to a 1b.
Bit [6:5]:
Reserved.
Bits [4:3]:
Arbiter Timeout Timer Value [2:0]
Number of clocks to wait for FRAME# to asset after GNT# is asserted
00 ATO time out after 16 clocks
01 ATO time out after 4 clocks
10 ATO time out after 8 clocks
11 ATO time out after 32 clocks
Bit 2:
Arbiter Timeout Timer Enable.
Bit 1:
CPU Park Enable. Otherwise the arbiter will park on the last master. 0=Enable.
Bit 0:
Bus Lock Enable. If set to 1b, this bit converts a PCI Lock cycle to a bus lock. If this bit is 0b,
the PCI arbiter ignores the LOCK# signal on the PCI bus.
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
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