參數(shù)資料
型號: W83C553F-G
英文描述: W83C553F-G Highly Integrated System I/O Controller for Power PCTM (South Bridge) QFP 208
中文描述: W83C553F接枝高度集成的系統(tǒng)I / O控制器的電力PCTM(南橋)QFP封裝208
文件頁數(shù): 145/159頁
文件大?。?/td> 3991K
代理商: W83C553F-G
W83C553F
Timing Diagrams
WINBOND SYSTEMS LABORATORY
142
Table 6-5. Miscellaneous Timing
Parameter
Values
Min
-
Max
Notes
t24
IDEIRQ[A:B] high to INT# low
or ISA IRQ high
50ns
Assumes that the interrupt path is enabled.
It could be disabled or
temporarily delayed due to read data in a
FIFO.
t25
t26
IDEIRQ[A:B] low to INT# float
or ISA IRQ low
-
30ns
-
20ns
50ns
RST# low to IDE_RST# low
50ns
t27
RST# high to IDE_RST# high
50ns
t28
t29
IDECS1# setup to
RST# high
-
IDECS1# hold from
RST# high.
0ns
-
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