參數(shù)資料
型號: W83C553F-G
英文描述: W83C553F-G Highly Integrated System I/O Controller for Power PCTM (South Bridge) QFP 208
中文描述: W83C553F接枝高度集成的系統(tǒng)I / O控制器的電力PCTM(南橋)QFP封裝208
文件頁數(shù): 41/159頁
文件大?。?/td> 3991K
代理商: W83C553F-G
W83C553F
3.10
The Memory Read command (C/BE[3:0]# = 6h during the address phase) is only used when operating as a bus master. It
will be used when transferring data to memory and the number of data phases is one half or less of the value programmed to
the Cache Line Size Register, or when reading less than 2 Dwords from memory. If the device needs to read more than 2
Dwords from memory, the Memory Read Line command is used. During the Memory Read cycle, the W83C553F issues a
PCI REQ# for the bus and, when PCI GNT# is asserted, reads one Dword from system memory. The bus is then released.
The data phase in Figure 3-6 takes two clock cycles, as determined by TRDY#. The W83C553F activates all byte enables,
even if some byte lanes do not contain valid data. It internally discards unnecessary bytes.
In slave mode, PCI-to-ISA memory reads are supported.
Electrical Specifications
WINBOND SYSTEMS LABORATORY
38
PCI Memory Read
Figure 3-6. Master Memory Read Timing
相關(guān)PDF資料
PDF描述
W83C554F W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
W83L519D Peripheral Miscellaneous
W86C451 UART
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W86F3448D LC86F3548A
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