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參數(shù)資料
| 型號(hào)： | W28J161TB90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 41/43頁 |
| 文件大小： | 1333K |
| 代理商： | W28J161TB90L |
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W28J161B/T
Publication Release Date: April 7, 2003
- 7 -
Revision A4
Pin Description, Continued
SYM.
TYPE
NAME AND FUNCTION
VPP
SUPPLY
BLOCK ERASE, FULL CHIP ERASE, WORD WRITE OR LOCK-BIT CONFIGURATION POWER
SUPPLY: For erasing array blocks, writing words or configuring lock-bits. With VPP ≤ VPPLK, memory
contents cannot be altered. Block erase, full chip erase, word write and lock-bit configuration with an
invalid VPP (see DC Characteristics) produce spurious results and should not be attempted. Applying
12V
±0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each block.
VPP may be connected to 12V ±0.3V for a total of 80 hours maximum.
VDD
SUPPLY
DEVICE POWER SUPPLY: Do not float any power pins. With VDD ≤ VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VDD voltage (see DC Characteristics)
produce spurious results and should not be attempted.
VSS
SUPPLY
GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Table 1
7. PRINCIPLES OF OPERATION
The W28J161B/T flash memory includes an on-chip WSM to manage block erase, full chip erase,
word write and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed
power supplies during block erase, full chip erase, word write and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from reset mode (see Bus Operations section), the device
defaults to read array mode. Manipulation of external memory control pins allow array read, standby
and output disable operations.
Status register and identifier codes can be accessed through the CUI independent of the VPP voltage.
High voltage on VPP enables successful block erase, full chip erase, word write and lock-bit
configurations. All functions associated with altering memory contents (block erase, full chip erase,
word write, lock-bit configuration, status and identifier codes) are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as input
to the WSM, which controls the block erase, full chip erase, word write and lock-bit configuration. The
internal algorithms are regulated by the WSM, including pulse repetition, internal verification and
margining of data. Addresses and data are internally latched during write cycles. Writing the
appropriate command outputs array data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block erase, full chip erase, word write and lock-
bit configuration can be stored in any block. This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read
Array command. Block erase suspend allows system software to suspend a block erase to read/write
data from/to blocks other than that which is suspend. Word write suspend allows system software to
suspend a word write to read data from any other flash memory array location.
Data Protection
When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, full chip
erase, word write or lock-bit configuration command sequences, provides protection from unwanted
operations even when high voltage is applied to VPP. All write functions are disabled when VDD is
below the write lockout voltage VLKO or when #RESET is at VIL. The device’s block locking capability
provides additional protection from inadvertent code or data alteration by gating block erase, full chip
erase and word write operations. Refer to Table 5 for write protection alternatives.
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